The Advanced Microcontroller Bus Architecture (AMBA) is a freely available, open standard to connect and manage functional blocks in a system-on-chip (SoC). It facilitates the right-first-time development of multiprocessor designs, with large numbers of controllers and peripherals.
AMBA specifications are royalty free and platform independent, and can be used with any processor architecture. Due to its widespread adoption, AMBA has a robust ecosystem of partners that ensures compatibility and scalability between IP components from different design teams and vendors.
For nearly three decades, AMBA has been a foundational open standard, and has been shipped in billions of devices.
The AMBA CHI specification defines the interfaces for the connection of fully coherent processors. It is appropriate for a wide range of applications that require coherency, including mobile, networking, automotive, and data centers. The AMBA CHI specification separates the protocol and transport layers to allow differing implementations to provide the optimal trade-off between performance, power, and area.
AMBA CHI C2C is an extension to CHI. It defines how the on-chip CHI protocol is packetized for transport over a chip(let)-to-chip(let) link. It targets advanced heterogeneous systems and Arm-based coherent SMP, providing a single and unified interface for device attachment for maximum interoperability.
The AMBA AXI specification defines the protocols to implement high-frequency, high-bandwidth interconnect designs across a wide range of applications, including mobile, consumer, networking, automotive, and embedded.
The AMBA AHB specification defines an interface protocol most widely used with Arm Cortex-M processors, for embedded designs and other low-latency SoCs.
AMBA APB is highly compact, low power, and allows configuration and low-bandwidth traffic to be isolated from high-performance interconnects. APB supports the low-bandwidth transactions required to access configuration registers and low- bandwidth data traffic in peripherals.
IP reuse requires a common standard while supporting a wide variety of SoCs with different power, performance, and area requirements. AMBA interfaces scale from simple, low-cost peripheral programming ports to fully coherent, high-bandwidth ports, spanning multiple interconnects and chip-to-chip interfacing.
CompatibilityAs an open standard specification, it helps ensure compatibility between IP components from different suppliers. Wide compatibility enables low-friction integration and design reuse, helping to reduce cost of ownership and to accelerate time-to-market. Compatible IP products vary from memory controllers, interconnects, trace solutions, GPUs, CPUs, peripherals, and many others.
Widely Adopted Open StandardAMBA is accepted as the standard for on-chip communication and is widely adopted across the industry. It has a long heritage of dependability and trust, and is used extensively in standards-based IP worldwide.
The wide adoption of AMBA throughout the semiconductor industry has driven a comprehensive market in third-party IP products and tools to support the development of AMBA-based systems.
The Learn the Architecture guides are free tutorials and how-to guides, designed to help hardware and software developers at all levels understand and use Arm technology. We have three guides available for AMBA, providing examples and allowing you to test your knowledge as you go.
AMBA 5 is the latest generation of freely available AMBA protocol specifications. It introduces the Coherent Hub Interface (CHI) architecture, which defines the interfaces to connect fully coherent processors and high-performance interconnects. AMBA 5 also introduces the AXI5, ACE5 and AHB5 protocols, which extend prior generations to include a number of performances and scalability features, and to align and complement CHI.
A chiplet is a silicon die that implements part of a system, designed to be combined to create larger and more complex systems that can be packaged and sold as a single component. This means you can assemble a silicon solution from several smaller dies, instead of one single larger monolithic die. The opportunity here is clear, but it also presents a new challenge for designers who will need to navigate interfaces which are not yet standardized, and many non-differentiating choices in chiplet partitioning.
AMBA has been enabling on-chip communication for nearly three decades, and we are pleased to be evolving AMBA with extensions for connecting chiplet-to-chiplet, initially starting with AMBA CHI.
“The release of the first public CHI C2C specification marks a significant step towards an open chiplet ecosystem and contributes to improvements in interoperability. We are pleased to partner with Arm on early AMBA developments as it will impact future versions of our high-bandwidth, low-latency network-on-chip interconnect IP technology including Ncore and FlexNoC. We look forward to further cooperation across the emerging chiplet ecosystem.”
- Laurent Moll, COO of Arteris
“With its disaggregated solutions in the form of chiplets, droplets, dielets, tiles and such, the More-than-Moore era presents significant opportunities and technology challenges for both designers and implementers. The need for standardized interfaces is paramount to facilitate communication between chiplets from a multitude of providers and to avoid building a tower of Babel. Cadence has a history of close collaboration with Arm on AMBA standards, and we’re pleased to build upon our partnership and bring the new AMBA CHI C2C standard to market in our IP and chiplet solutions encompassing flows, reference designs and customer designs. This important new standard will be a key ecosystem enabler and should promote an open chiplet marketplace, which is still in its nascent stage.”
- David Glasco, VP of R&D for the Silicon Solutions Group at Cadence
“Fujitsu considers chiplets as essential technology for future processor architectures. We’re already adopters of the open, foundational AMBA specifications, and the latest AMBA CHI C2C specification is a step-change in establishing how to transport data efficiently in low-latency off-chip use cases, such as chiplet-to-chiplet. We’re excited to see how this will enable the chiplet ecosystem.”
- Toshio Yoshida, Executive Director, Advanced Technology Development Unit, Fujitsu
“Intel® has long envisioned a “chiplet revolution,” which was the motivation for our introducing the UCIe protocol to the industry in 2022. We are pleased to see the industry’s growth and adoption of UCIe™, advanced packaging technologies, and standards-based protocol mapping. Along with UCIe, the standardization and release of the AMBA CHI C2C specification is a critical building block for the industry’s drive toward chiplet based architectures and we are excited to continue our collaboration with Arm.”
- Bob Brennan, IFS, VP, Customer Solutions Engineering, Intel
“The AMBA CHI C2C specification will enable efficient chip-to-chip interconnectivity, allowing the creation of powerful AI systems that support coherency and confidential compute for a wide variety of use cases, from chiplets to off-package connectivity. Our significant work over the past four years to advance this new standard, in collaboration with Arm and other ecosystem partners, will help propel the industry forward and drive breakthroughs in AI and accelerated computing.”
- Ashish Karandikar, Vice President of Hardware Engineering at NVIDIA
“Chiplets provide a key architectural solution for the acceleration of computing performance needed by AI and other advanced workloads. As longstanding members of the AMBA ecosystem, we are excited to support the AMBA CHI C2C specification as an important enabling technology for next-generation chiplet designs.”
- Neeraj Paliwal, General Manager of Silicon IP, Rambus
“Chiplets will definitely be an effectively solution in the semiconductor industry for next decade to address dramatically cost of high performance SoC with advanced process node. Together, UCIe PHY will be used as the physical layer standard for chiplets interconnect and AMBA CHI C2C will be used as an open standard for the protocol layer for chiplets interconnect to extend on-chip CHI to multi-chiplet interconnect. AMBA CHI C2C not only ensure Arm architecture features like security, virtualization, etc. extend to multi-chiplet boundary and also lower chiplet-to-chiplet latency without additional protocol transition. AMBA CHI C2C as a fundamental protocol to enable compute chiplets, IO chiplets and accelerator chiplets interoperable in extensive widely Arm architecture ecosystem.”
- Owen Shi, Vice President of Sanechips
“Siemens EDA is pleased to support the development of AMBA, taking AMBA CHI C2C protocol to the growing chiplet ecosystem, which is an area of Siemens’ focus with our Avery Verification IP and Veloce hardware-assisted verification solutions.”
- Abhi Kolpekwar, VP and General Manager of Digital Verification Technology at Siemens EDA
“Chiplet-based architecture for compute could be a game-changer for Europe in the era of ubiquitous AI. In this context, one of the main challenges is to guarantee interoperability and composability at pace. The new AMBA CHI C2C specification will be key to achieving this. We’ve been proud to collaborate with Arm and the ecosystem in its development and release.”
- Philippe Notton, CEO & Founder of SiPearl
“With the shift to multi-die systems, designers require standard interfaces to maximize chiplet interoperability and minimize latency. Synopsys worked closely with Arm and its ecosystem to develop and optimize the CHI C2C specification. Supported by the complete Synopsys UCIe IP solution, this new chiplet standard will accelerate time-to-market and reduce die-to-die latency for a wide array of high-performance applications using Arm technology. This announcement builds on our longstanding technical engagement with Arm to optimize interoperability, performance, and bandwidth of systems that integrate Arm processors and Synopsys IP.”
- John Koeter, Senior Vice President of Marketing and Strategy for IP at Synopsys
